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WM8141 12-bit 6MSPS CIS/CCD Analogue Front End/Digitiser
Production Data, October 2000, Rev 3.0
DESCRIPTION
The WM8141 is a 12-bit analogue front end/digitiser that processes and digitises the analogue output signals from CCDs or Contact Image Sensors (CIS). The device can be operated as either a three channel or a single channel device at pixel sample rates of up to 6MSPS. The device has both external and programmable internal black level reference options for CIS operation. The WM8141 runs off a single supply voltage of either 3.3V or 5V. Alternatively, the device can be operated from split 5V core and 3.3V digital interface supplies. The WM8141 includes three analogue signal processing channels each of which contains reset level clamping, correlated double sampling and programmable offset and gain adjust facilities. Each of these channels is time multiplexed into a single high-speed 12-bit resolution ADC, which digitises the pixel image information. The digital data output is available to the user in either 12-bit parallel or 8/6/4-bit wide multiplexed formats. The internal control registers are programmable via a convenient serial or parallel digital interface. The WM8141 typically consumes only 45mA and less than 10A when in power down mode.
FEATURES
* * * * * * * * * * * * * * 12-bit resolution ADC 6MSPS conversion rate at 5V supply 5V or 3.3V single supply or 5V/3.3V dual supply operation Single or 3 channel operation Correlated double sampling Programmable gain (8-bit resolution) Programmable offset adjust (8-bit resolution) 12-bit parallel or 8/6/4-bit wide multiplexed output bus Internally generated voltage references External or internal reference for CIS operation Low power - 225mW typical at 5V supply Interface and timing compatible with WM8143, WM8144 and WM8142 devices Drop in replacement for WM8143-12 32-pin TQFP package
APPLICATIONS
* * * * * Flatbed and sheetfeed scanners USB compatible scanners Multi-function peripherals CCD sensor interface Contact image sensor (CIS) interface
BLOCK DIAGRAM
VRLC/VBIAS (18) VSMP (27) MCLK (28) AVDD (12) DVDD1 DVDD2 (14) (32) VRT VRX VRB (16) (17) (15)
CL
RS
VS
TIMING CONTROL
R G B
VREF/BIAS
M U X 8
WM8141 (22) OEB
OFFSET DAC + PGA
8
RINP (21)
RLC
M U X
CDS
R G B M U X
+ I/P SIGNAL POLARITY ADJUST M U X 12 BIT ADC DATA I/O PORT
GINP (20)
RLC
CDS
8
+ OFFSET DAC
PGA
8
+ I/P SIGNAL POLARITY ADJUST
(30) OP[0] (31) OP[1] (1) OP[2] (2) OP[3] (3) OP[4] (4) OP[5] (5) OP[6] (6) OP[7] (7) OP[8] (8) OP[9] (9) OP[10] (10) OP[11]/SDO
BINP (19)
RLC
CDS
8
+ OFFSET DAC
PGA
8
+ I/P SIGNAL POLARITY ADJUST CONFIGURABLE SERIAL/ PARALLEL CONTROL INTERFACE (23) SEN/STB (25) SCK/RNW (24) SDI/DNA (26) RLC/ACYC (11) NRESET
RLC DAC
4
(13) AGND
(29) DGND
WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk
Production Data Datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and Conditions.
2000 Wolfson Microelectronics Ltd.
WM8141 PIN CONFIGURATION
RLC/ACYC DVDD2 DGND VSMP MCLK OP[1] OP[0] SCK/RNW
Production Data
ORDERING INFORMATION
DEVICE WM8141CFT/V TEMP. RANGE 0 to 70C PACKAGE 32-pin TQFP
32 31 30 OP[2] OP[3] OP[4] OP[5] OP[6] OP[7] OP[8] OP[9] 1 2 3 4 5 6 7 8 9 10 11
29 28
27 26 25 24 23 22 21 20 19 18 17 14 15 16
SDI/DNA SEN/STB OEB RINP GINP BINP VRLC/VBIAS VRX
12 13
OP[11]/SDO
OP[10]
NRESET
DVDD1
AVDD
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 NAME OP[2] OP[3] OP[4] OP[5] OP[6] OP[7] OP[8] OP[9] OP[10] OP[11]/ SDO NRESET AVDD AGND DVDD1 VRB VRT VRX VRLC/ VBIAS BINP GINP RINP OEB TYPE Digital output Digital output Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital IO Digital input Supply Supply Supply Analogue output Analogue output Analogue output Analogue IO Reset input, active low. This signal forces a reset of all internal registers and selects whether the serial or parallel control bus is used (see SEN/STB). Analogue supply (3.3/5V) for CDS, PGA and OFFSET blocks. This must be operated at the same potential as DVDD1. Analogue ground (0V). Digital supply (3.3/5V) for logic and clock generator. This must be operated at the same potential as AVDD. Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor. Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. Blue channel input video. Green channel input video. Red channel input video. Output Hi-Z control: all outputs disabled when OEB = 1. DESCRIPTION Hi-Z digital 12-bit bi-directional bus. There are several modes: Hi-Z: when OEB = 1. 12-bit output: 12-bit data is output on OP[11:0]. 8-bit multiplexed output: data is output on OP[11:4] at 2 ADC conversion rate. 6-bit multiplexed output: data is output on OP[11:6] at 2 ADC conversion rate. 4-bit multiplexed output: data is output on OP[11:8] at 4 ADC conversion rate. Input 8-bit: control data is input on OP[11:4] in parallel mode when SCK/RNW = 0, and SEN/STB = 0. Output 8-bit: register read back data is output in parallel on OP[11:4] when SCK/RNW = 1, and SEN/STB = 0, or in serial on pin SDO when SEN/STB = 1.
19 20 21 22
Analogue input Analogue input Analogue input Digital input
WOLFSON MICROELECTRONICS LTD
AGND
VRB
VRT
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Production Data PIN 23 NAME SEN/STB TYPE Digital input DESCRIPTION Serial Interface: Enable pulse, active high.
WM8141
Parallel Interface: Strobe, active low.
Latched on NRESET rising edge: If Low then device control is via serial interface, if High then device control is via parallel interface. 24 25 SDI/DNA SCK/RNW Digital input Digital input Serial Interface: Serial input data signal. Serial Interface: Serial clock signal. Parallel Interface: High = data, Low = address. Parallel Interface: High = OP[11:4] is output bus, Low = OP[11:4] is input bus (Hi-Z) ACYC, auto-cycles between RINP, GINP, BINP when in line by line mode.
26
RLC/ ACYC VSMP MCLK DGND OP[0] OP[1] DVDD2
Digital input
Selects whether Reset Level Clamp is applied (active high). If RLC is required on every pixel then this pin can be tied high. Video sample synchronisation pulse.
27 28 29 30 31 32
Digital input Digital input Supply Digital output Digital output Supply
Master clock. This clock is applied at N times the input pixel rate (N = 8, 6, 3 or 2 depending on the input sampling mode). Digital ground (0V). Hi-Z digital 12-bit bi-directional bus, see description for pins OP[2] to OP[11]/SDO. Digital supply (3.3/5V) for all digital pins.
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specifications A112-A and A113-B, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. CONDITION Analogue supply voltage: AVDD Digital supply voltages: DVDD1, DVDD2 Digital ground: DGND Analogue ground: AGND Digital inputs, digital outputs and digital pins Analogue inputs (RINP, GINP, BINP) Other pins Operating temperature range: TA Storage temperature Package body temperature (soldering, 10 seconds) Package body temperature (soldering, 2 minutes) Notes: 1. 2. 3. GND denotes the voltage of any ground pin. AGND and DGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. AVDD and DVDD1 pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. MIN GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V 0C -50C MAX GND + 7V GND + 7V GND + 0.3V GND + 0.3V DVDD2 + 0.3V AVDD + 0.3V AVDD + 0.3V +70C +150C +240C +183C
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WM8141 RECOMMENDED OPERATING CONDITIONS
CONDITION Operating temperature range Digital supply voltages (5V operation) Digital supply voltages (3.3V operation) Analogue supply voltage (5V operation) Analogue supply voltage (3.3V operation) SYMBOL TA DVDD1, DVDD2 DVDD1, DVDD2 AVDD AVDD MIN 0 4.75 2.97 4.75 2.97 5 3.3 5 3.3 TYP MAX 70 5.25 3.63 5.25 3.63
Production Data
UNITS C V V V V
POSSIBLE POWER SUPPLY COMBINATIONS
COMBINATION 1 2 3 AVDD, DVDD1 (VOLTS) 5 5 3.3 DVDD2 (VOLTS) 5 3.3 3.3
ELECTRICAL CHARACTERISTICS
ANALOGUE CHARACTERISTICS (5V OPERATION)
Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 12MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS Max Gain Min Gain VIN Gain = 0dB; PGA[7:0] = 4B(hex) Gain = 0dB; PGA[7:0] = 4B(hex) DNL INL 0 20 20 0.5 2 1 VRT VRB VRX VRTB 2.70 1.25 0.60 1.4 2.85 1.35 0.65 1.5 1 3.00 1.45 0.70 1.6 1 MIN TYP MAX UNIT
Overall System Specification Including CDS, PGA, OFFSET and ADC Functions. No Missing Codes Guaranteed. Full-scale input voltage range (see Note 1) Input signal limits (see Note 2) Full-scale transition error Zero-scale transition error Differential non-linearity Integral non-linearity Channel to channel gain matching References Upper reference voltage Lower reference voltage Input return bias voltage Diff. reference voltage (VRT-VRB) Output resistance VRT, VRB, VRX V V V V 0.4 4.08 AVDD Vp-p Vp-p V mV mV LSB LSB %
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Production Data
WM8141
Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 12MHz unless otherwise stated. PARAMETER VRLC/Reset-Level Clamp (RLC) RLC switching impedance VRLC short-circuit current VRLC output resistance VRLC Hi-Z leakage current RLCDAC resolution RLCDAC step size, RLCDAC = 0 RLCDAC step size, RLCDAC = 1 RLCDAC output voltage at code 0(hex), RLCDACRNG = 0 RLCDAC output voltage at code 0(hex), RLCDACRNG = 1 RLCDAC output voltage at code F(hex) RLCDACRNG, = 0 RLCDAC output voltage at code F(hex), RLCDACRNG = 1 Resolution Differential non-linearity Integral non-linearity Step size Output voltage Programmable Gain Amplifier Resolution Gain Max gain, each channel Min gain, each channel Gain error, each channel Supply Currents Total supply current - active Total analogue supply current - active Digital logic supply current, DVDD1 - active Digital I/O supply current, DVDD2 - active Supply current - full power down mode Notes: 1. 2. IAVDD 45 42 2 1 10 65 mA mA mA mA A GMAX GMIN 8
208 283 - PGA[7 : 0]
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50 5 2 1 4 VRLCSTEP VRLCSTEP VRLCBOT VRLCBOT VRLCTOP VRLCTOP 0.24 0.16 0.4 0.25 4.2 2.85
mA A bits V/step V/step V V V V
Offset DAC, Monotonicity Guaranteed 8 DNL INL Code 00(hex) Code FF(hex) 0.1 0.25 2.04 -260 +260 0.5 1 bits LSB LSB mV/step mV mV bits V/V V/V V/V 5 %
7.4 0.74 1
Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain. Input signal limits are the limits within which the full-scale input voltage signal must lie.
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WM8141
ANALOGUE CHARACTERISTICS (3.3V OPERATION)
Production Data
Test Conditions AVDD = DVDD1 = DVDD2 = 2.97V to 3.63V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 8MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS Max Gain Min Gain VIN Gain = 0dB; PGA[7:0] = 4B(hex) Gain = 0dB; PGA[7:0] = 4B(hex) DNL INL 0 20 20 0.5 2 1 VRT VRB VRX VRTB 1.625 0.900 0.60 0.65 1.725 0.975 0.65 0.75 1 140 5 2 <0.1 4 VRLCSTEP VRLCSTEP VRLCBOT VRLCBOT VRLCTOP VRLCTOP 0.16 0.09 0.25 0.2 2.75 1.7 1.825 1.050 0.70 0.85 MIN TYP MAX UNIT
Overall System Specification Including CDS, PGA, OFFSET and ADC Functions. Full-scale input voltage range (see Note 1) Input signal limits (see Note 2) Full-scale transition error Zero-scale transition error Differential non-linearity Integral non-linearity Channel to channel gain matching References Upper reference voltage Lower reference voltage Input return bias voltage Diff. reference voltage (VRT-VRB) Output resistance VRT, VRB, VRX VRLC/Reset-Level Clamp (RLC) RLC switching impedance VRLC short-circuit current VRLC output resistance VRLC Hi-Z leakage current RLCDAC resolution RLCDAC step size, RLCDAC = 0 RLCDAC step size, RLCDAC = 1 RLCDAC output voltage at code 0(hex), RLCDACRNG = 0 RLCDAC output voltage at code 0(hex), RLCDACRNG = 1 RLCDAC output voltage at code F(hex), RLCDACRNG = 0 RLCDAC output voltage at code F(hex), RLCDACRNG = 1 Offset DAC Resolution Differential non-linearity Integral non-linearity Step size Output voltage Programmable Gain Amplifier Resolution Gain Max gain, each channel Min gain, each channel Gain error, each channel Notes: 1. 2. GMAX GMIN 8
208 283 - PGA[7 : 0]
0.2 2.04 AVDD
Vp-p Vp-p V mV mV LSB LSB % V V V V mA A bits V/step V/step V V V V
8 DNL INL Code 00(hex) Code FF(hex) 0.1 0.25 1.02 -130 +130
bits LSB LSB mV/step mV mV bits V/V V/V V/V %
7.4 0.74 1
Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain. Input signal limits are the limits within which the full-scale input voltage signal must lie.
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Production Data
WM8141
Test Conditions AVDD = DVDD1 = DVDD2 = 2.97V to 3.63V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 8MHz unless otherwise stated. PARAMETER Supply Currents Total supply current - active Total analogue supply current - active Digital logic supply current, DVDD1 - active Digital I/O supply current, DVDD2 - active Supply current - full power down mode IAVDD 43 40 2 1 10 mA mA mA mA A SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL CHARACTERISTICS
Test Conditions AVDD = DVDD1 = DVDD2 = 2.97V to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 12MHz unless otherwise stated. PARAMETER DIGITAL SPECIFICATIONS Digital Inputs High level input voltage Low level input voltage High level input current Low level input current Input capacitance Digital Outputs High level output voltage Low level output voltage High impedance output current Digital IO Pins Applied high level input voltage Applied low level input voltage High level output voltage Low level output voltage Low level input current High level input current Input capacitance High impedance output current VIH VIL VOH VOL IIL IIH CI IOZ 5 1 IOH = 1mA IOL = 1mA DVDD2 - 0.5 0.5 1 1 0.8 DVDD2 0.2 DVDD2 V V V V A A pF A VOH VOL IOZ IOH = 1mA IOL = 1mA DVDD2 - 0.5 0.5 1 V V A VIH VIL IIH IIL CI 5 0.8 DVDD2 0.2 DVDD2 1 1 V V A A pF SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
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WM8141
INPUT VIDEO SAMPLING
tPER MCLK tVSMPSU VSMP INPUT tVSU VIDEO tVH tRSU tRH tVSMPH tMCLKH tMCLKL
Production Data
Figure 1 Input Video Timing Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 12MHz unless otherwise stated PARAMETER MCLK period MCLK high period MCLK low period VSMP set-up time VSMP hold time Video level set-up time Video level hold time Reset level set-up time Reset level hold time Notes: 1. 2. SYMBOL tPER tMCLKH tMCLKL tVSMPSU tVSMPH tVSU tVH tRSU tRH TEST CONDITIONS MIN 83.3 37.5 37.5 10 10 10 15 10 15 TYP MAX UNITS ns ns ns ns ns ns ns ns ns
tVSU and tRSU denote the set-up time required after the input video signal has settled. Parameters are measured at 50% of the rising/falling edge.
OUTPUT DATA TIMING
MCLK tPD
OP[11:0]
Figure 2 Output Data Timing
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Production Data
WM8141
OEB tPZE OP[11:0] Hi-Z tPEZ Hi-Z
Figure 3 Output Data Enable Timing Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 12MHz unless otherwise stated PARAMETER Output propagation delay Output enable time Output disable time SYMBOL tPD tPZE tPEZ TEST CONDITIONS IOH = 1mA, IOL = 1mA MIN TYP MAX 75 50 25 UNITS ns ns ns
SERIAL INTERFACE
tSPER SCK tSSU SDI tSCE SEN tSESD SDO MSB tSCSD tSCSDZ LSB tSEW tSEC tSH tSCKL tSCKH
Figure 4 Serial Interface Timing Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 12MHz unless otherwise stated PARAMETER SCK period SCK high SCK low SDI set-up time SDI hold time SCK to SEN set-up time SEN to SCK set-up time SEN pulse width SEN low to SDO out SCK low to SDO out SCK low to SDO high impedance SYMBOL tSPER tSCKH tSCKL tSSU tSH tSCE tSEC tSEW tSESD tSCSD tSCSDZ TEST CONDITIONS MIN 83.3 37.5 37.5 10 10 20 20 50 35 35 25 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns
Note: Parameters are measured at 50% of the rising/falling edge. WOLFSON MICROELECTRONICS LTD
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WM8141
PARALLEL INTERFACE
tSTB STB tASU Hi-Z OP[11:4]
ADC DATA OUT ADDRESS IN DATA IN
Production Data
tAH
tDSU
tDH Hi-Z
tSTDO
ADC DATA OUT
tSTAO
REG. DATA OUT ADC DATA OUT
tADLS DNA tOPZ RNW
tADLH
tADHS
tADHH
tOPD
Figure 5 Parallel Interface Diagram Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 12MHz unless otherwise stated PARAMETER RNW low to OP[11:4] tri-state. Address set-up time to STB low DNA low set-up time to STB low Strobe low time Address hold time from STB high DNA low hold time from STB high Data set-up time to STB low DNA high set-up time to STB low Data hold time from STB high Data high hold time from STB high RNW high to OP[11:4] output Data output propagation delay from STB low ADC data out propagation delay from STB high SYMBOL tOPZ tASU tADLS tSTB tAH tADLH tDSU tADHS tDH tADHH tOPD tSTDO tSTAO 0 10 50 10 10 0 10 10 10 35 35 35 TEST CONDITIONS MIN TYP MAX 20 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: Parameters are measured at 50% of the rising/falling edge.
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Production Data
WM8141
DEVICE DESCRIPTION
INTRODUCTION
A block diagram of the device showing the signal path is presented on Page 1. The WM8141 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then processes the sampled video signal with respect to the video reset level or an internally/externally generated reference level using either one or three processing channels. Each processing channel consists of an Input Sampling block with optional Reset Level Clamping (RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit Programmable Gain Amplifier (PGA). The ADC then converts each resulting analogue signal to a 12-bit digital word. The digital output from the ADC is presented on a 12-bit wide bi-directional bus, with optional 8+4-bit, 6+6-bit or 4+4+4-bit multiplexed formats. On-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. These registers are programmable via serial or parallel interfaces.
INPUT SAMPLING
The WM8141 can sample and process one to three inputs through one or three processing channels as follows: Colour Pixel-by-Pixel: The three inputs (RINP, GINP and BINP) are simultaneously sampled for each pixel and a separate channel processes each input. The signals are then multiplexed into the ADC, which converts all three inputs within the pixel period. Monochrome: A single chosen input (RINP, GINP, or BINP) is sampled, processed by the corresponding channel, and converted by the ADC. The choice of input and channel can be changed via the control interface, e.g. on a line-by-line basis if required. Colour Line-by-Line: A single chosen input (RINP, GINP, or BINP) is sampled and multiplexed into the red channel for processing before being converted by the ADC. The input selected can be switched in turn (RINP GINP BINP RINP...) together with the PGA and Offset DAC control registers by pulsing the RLC/ACYC pin. This is known as auto-cycling. Alternatively, other sampling sequences can be generated via the control registers. This mode causes the blue and green channels to be powered down. Refer to the Line-by-Line Operation section for more details.
RESET LEVEL CLAMPING (RLC)
To ensure that the signal applied to the WM8141 lies within its input range (0V to AVDD) the CCD output signal is usually level shifted by coupling through a capacitor, CIN. The RLC circuit clamps the WM8141 side of this capacitor to a suitable voltage during the CCD reset level. A typical input configuration is shown in Figure 5. A clamp pulse, CL, is generated from MCLK and VSMP by the Timing Control Block. When CL is active the voltage on the WM8141 side of CIN, at RINP, is forced to the VRLC/VBIAS voltage (VVRLC ) by switch 1. When the CL pulse turns off, the voltage at RINP initially remains at VVRLC but any subsequent variation in sensor voltage (from reset to video level) will couple through CIN to RINP. RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to the CDS/non-CDS Processing section.
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WM8141
Production Data
RLC/ACYC
MCLK
VSMP
TIMING CONTROL CL RS VS
FROM CONTROL INTERFACE
CIN
S/H +
RINP 1
RLC
2
+
S/H CDS INPUT SAMPLING BLOCK FOR RED CHANNEL
TO OFFSET DAC
EXTERNAL VRLC VRLC/ VBIAS
CDS 4-BIT RLC DAC VRLCEXT
FROM CONTROL INTERFACE
Figure 6 Reset Level Clamping and CDS Circuitry If auto-cycling is not required, RLC can be selected by pin RLC/ACYC. Figure 6 illustrates control of RLC for a typical CCD waveform, with CL applied during the reset period. The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0] (Figure 7). If auto-cycling is required, pin RLC/ACYC is no longer available for this function and control bit RLCINT determines whether clamping is applied.
MCLK
VSMP
RLC/ACYC
1
X Programmable Delay
X
0
X
X
0
CL (CDSREF = 01)
INPUT VIDEO
RGB
RGB RLC on this Pixel
RGB No RLC on this Pixel
Figure 7 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
CDS/NON-CDS PROCESSING
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel common mode noise. For CDS operation, the video level is processed with respect to the video reset level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must be set to 1 (default), this controls switch 2 (Figure 6) and causes the signal reference to come from the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by programming control bits CDSREF[1:0], as shown in Figure 8.
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Production Data
WM8141
MCLK VSMP
VS RS/CL (CDSREF = 00) RS/CL (CDSREF = 01) RS/CL (CDSREF = 10) RS/CL (CDSREF = 11)
Figure 8 Reset Sample and Clamp Timing For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this mode.
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset for each channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0]. In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order (Red Green Blue Red...) by pulsing the ACYC/RLC pin, or controlled via the FME, ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-line Operation section for more details.
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA must be offset to match the full-scale range of the ADC. For negative-going input signals, a black level (zero differential) output from the PGA should be offset to the top of the ADC range. For positive going input signal the black level should be offset to the bottom of the ADC range. This is achieved by writing to control bits PGAFS[1:0].
OVERALL SIGNAL FLOW SUMMARY
Figure 9 represents the processing of the video signal through the WM8141.
OUTPUT INVERT BLOCK
INPUT SAMPLING OFFSET DAC PGA BLOCK BLOCK BLOCK
ADC BLOCK
V1
VIN CDS = 1 VRESET CDS = 0 VVRLC RLCEXT=1 RLCEXT=0
Offset DAC
V2
+ +
+
-
X
V3
analog
x (4095/VFS) +0 if PGAFS[1:0]=11 +4095 if PGAFS[1:0]=10 +2047 if PGAFS[1:0]=0x
D1
digital
D2
OP[11:0]
D2 = D1 if INVOP = 0 D2 =4095-D1 if INVOP = 1 PGA gain A = 208/(283-PGA[7:0]) 260mV*(DAC[7:0]-127.5)/127.5 VIN is RINP or GINP or BINP VRESET is VIN sampled during reset clamp VVRLC is voltage applied to VRLC pin CDS, RLCEXT,RLCV[3:0], DAC[7:0], PGA[7:0], PGAFS[1:0] and INVOP are set by programming internal control registers. CDS=1 for CDS, 0 for non-CDS
RLC DAC
VRLCSTEP*RLCV[3:0] + VRLCBOT
Figure 9 Overall Signal Flow
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Production Data The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC, optionally set via the RLC DAC. The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the black level of the input signal towards 0V, producing V2. The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range, outputting voltage V3. The ADC BLOCK then converts the analogue signal, V3, to a 12-bit unsigned digital output, D1. The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.
CALCULATING OUTPUT FOR ANY GIVEN INPUT
The following equations describe the processing of the video and reset level signals through the WM8141.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the input video. V1 = VIN - VRESET ................................................................... Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead. V1 = VIN - VVRLC .................................................................... Eqn. 2
If RLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS. If RLCEXT = 0, VVRLC is the output from the internal RLC DAC. VVRLC = (VRLCSTEP RLCV[3:0]) + VRLCBOT ................................. Eqn. 3
VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V1 is added to the Offset DAC output. V2 = V1 + {260mV (DAC[7:0]-127.5) } / 27.5 ....................... Eqn. 4
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain, V3 = V2 208/(283- PGA[7:0]) .............................................. Eqn. 5
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 12-bit unsigned number, with input range configured by PGAFS[1:0]. D1[11:0] = INT{ (V3 /VFS) 4095} + 2047 D1[11:0] = INT{ (V3 /VFS) 4095} D1[11:0] = INT{ (V3 /VFS) 4095} + 4095 PGAFS[1:0] = 00 or 01 ...... Eqn. 6 PGAFS[1:0] = 11 ............... Eqn. 7 PGAFS[1:0] = 10 ............... Eqn. 8
where the ADC full-scale range, VFS = 3V at AVDD=5V and VFS = 1.5V at AVDD=3.3V
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP. D2[11:0] = D1[11:0] D2[11:0] = 4095 - D1[11:0] (INVOP = 0) ...................... Eqn. 9 (INVOP = 1) ...................... Eqn. 10
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WM8141
The digital data output from the ADC is available to the user in either 12-bit parallel or 8/6/4-bit wide multiplexed formats by setting control bits MUXOP[1:0]. Latency of valid output data with respect to VSMP is programmable by writing to control bits DEL[1:0]. The latency for each mode is shown in the Mode Timing Diagrams section. Figure 10 shows the output data formats for Modes 1 - 2 and 4 - 6. Figure 11 shows the output data formats for Mode 3. Table 1 summarises the output data obtained for each format.
OUTPUT FORMATS
MCLK
MCLK
12-BIT PARALLEL OUTPUT
A
12-BIT PARALLEL OUTPUT
A
8+4 AND 6+6-BIT OUTPUT
A
B
8+4 AND 6+6-BIT OUTPUT
A
B
4+4+4-BIT OUTPUT
A
B
C
F
4+4+4-BIT OUTPUT
ABABCF
Figure 10 Output Data Formats (Modes 1 - 2, 4 - 6) OUTPUT FORMAT 12-bit parallel 8+4-bit multiplexed 6+6-bit multiplexed 4+4+4-bit multiplexed (nibble) MUXOP[1:0] 00 01 10 11 OUTPUT PINS OP[11:0] OP[11:4] OP[11:4] OP[11:8]
Figure 11 Output Data Formats (Mode 3)
OUTPUT A = d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0 A = d11, d10, d9, d8, d7, d6, d5, d4 B = d3, d2, d1, d0, PNS, CC[1], CC[0], OVRNG A = d11, d10, d9, d8, d7, d6, CC[1], CC[0] B = d5, d4, d3, d2, d1, d0, PNS, OVRNG A = d11, d10, d9, d8 B = d7, d6, d5, d4 C = d3, d2, d1, d0 F = PNS, CC[1], CC[0], OVRNG
Table 1 Details of Output Data Shown in Figures 9 and 10
FLAGS
The following flags are output during multiplexed modes: PNS indicates whether the control interface is operating in parallel or serial, 1 = parallel, 0 = serial. CC[1] and CC[0] indicate from which input the current output was sampled: INPUT RINP GINP BINP CC[1] 0 0 1 CC[0] 0 1 0
Table 2 Input Sampled Flags CC[1:0] OVRNG indicates that the current output data was produced by an input signal that exceeded the input range limit of the device. 1 = out of range, 0 = within range.
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CONTROL INTERFACE
Production Data
The internal control registers are programmable via the serial or parallel digital control interface. The register contents can also be read back via the parallel interface on OP[11:4], or via the serial interface on pin OP[11]/SDO.
SERIAL INTERFACE: REGISTER WRITE
Figure 12 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK. When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode.
SCK
SDI
a5
0
a3
a2
a1
a0
b7
b6
b5
b4
b3
b2
b1
b0
Address SEN
Data Word
Figure 12 Serial Interface Register Write
SERIAL INTERFACE: REGISTER READ-BACK
Figure 13 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge of SCK). Note that pin SDO is shared with an output pin, OP[11], therefore OEB should always be held low when register read-back data is expected on this pin. The next word may be read in to SDI while the previous word is still being output on SDO.
SCK
SDI
a5 1 a3 a2 a1 a0
x
x
x
x
x
x
x
x
Address SEN SDO/ OP[11] OEB
Data Word
d7 d6 d5 d4 d3 d2 d1 d0
Output Data Word
Figure 13 Serial Interface Register Read-back
PARALLEL INTERFACE: REGISTER WRITE
Figure 13 shows register write in parallel mode. The parallel interface uses bits OP[11:4] of the output bus and the STB, DNA and RNW pins. Pin RNW must be low during a write operation. The DNA pin defines whether the data byte is address (low) or data (high). The 6-bit address (a5, 0, a3, a2, a1, a0) is input into OP[9:4], LSB into OP[4], (OP[10] and OP[11] are ignored) when DNA is low, then the 8-bit data word is input into OP[11:4], LSB into OP[4], when DNA is high. The data bus OP[11:4] for both address and data is clocked in on the falling edge of STB. Note all valid registers have address bit a4 equal to 0.
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WM8141
STB
Driven by WM8141 Driven Externally Hi-Z Address Data Hi-Z Driven by WM8141 Normal Output Data
OP[11:4]
Normal Output Data
DNA
RNW
Figure 14 Parallel Interface Register Write
PARALLEL INTERFACE: REGISTER READ-BACK
Figure 15 shows register read-back in parallel mode. Read-back is initiated by writing the 6-bit address (a5, 1, a3, a2, a1, a0) into OP[9:4] by pulsing the STB pin low. Note that a4 = 1 and pins RNW and DNA are low. When RNW and DNA are high and STB is strobed again, the contents (d7, d6, d5, d4, d3, d2, d1, d0) of the corresponding register (a5, 0, a3, a2, a1, a0) will be output on OP[11:4], LSB on pin OP[4]. Until STB is pulsed low, the current contents of the ADC (shown as Normal Output Data) will be present on OP[11:4]. Note that the register data becomes available on the output data pins so OEB should be held low when read-back data is expected.
STB
Driven by WM8141 Hi-Z Driven Externally Address Hi-Z Read Data Driven by WM8141 Normal Output Data
OP[11:4]
Normal Output Data
DNA
RNW
Figure 15 Parallel Interface Register Read-back
TIMING REQUIREMENTS
To use this device a master clock (MCLK) of up to 12MHz and a per-pixel synchronisation clock (VSMP) of up to 6MHz are required. These clocks drive a timing control block, which produces internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum sample rates for the various modes are shown in Table 5.
PROGRAMMABLE VSMP DETECT CIRCUIT
The VSMP input is used to determine the sampling point and frequency of the WM8141. Under normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling frequency (as shown in the mode timing diagrams) and the input sample will be taken on the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal may not be readily available. The programmable VSMP detect circuit in the WM8141 allows the sampling point to be derived from any signal of the correct frequency, such as a CCD shift register clock, when applied to the VSMP pin. When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge (determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse. This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits. Figure 16 shows the internal VSMP pulses that can be generated by this circuit for a typical clock input signal. The internal VSMP pulse is then applied to the timing control block in place of the normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising MCLK edge after this internal VSMP pulse, as shown in the mode timing diagrams. WOLFSON MICROELECTRONICS LTD
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MCLK INPUT PINS VSMP POSNNEG = 1 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP POSNNEG = 0 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP
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Figure 16 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit
REFERENCES
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin VRLC/VBIAS
POWER SUPPLY
The WM8141 can run off either 3.3V or 5V single supplies or from split 5V (core) and 3.3V (digital interface) supplies.
POWER MANAGEMENT
Power management for the device is performed via the Control Interface. The device can be powered on or off completely by the EN bit. Alternatively, when control bit SELPD is high, only blocks selected by further control bits (SELDIS[3:0]) are powered down. This allows the user to optimise power dissipation in certain modes, or to define an intermediate standby mode to allow a quicker recovery into a fully active state. In Line-by-line operation, the green and blue channel PGAs are automatically powered down. All the internal registers maintain their previously programmed value in power down modes and the Control Interface inputs remain active. Table 3 summarises the power down control bit functions. EN 0 1 X SELDPD 0 0 1 Device completely powers down. Device completely powers up. Blocks with respective SELDIS[3:0] bit high are disabled.
Table 3 Power Down Control
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LINE-BY-LINE OPERATION
Certain linear sensors (e.g Contact Image Sensors) give colour output on a line-by-line basis. i.e a full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to accommodate this type of signal the WM8141 can be set into Monochrome mode, with the input channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8141 can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is set the green and blue processing channels are powered down and the device is forced internally to only operate in MONO mode (because only one colour is sampled at a time) through the red channel. Figure 17 shows the signal path when operating in colour line-by-line mode.
VRLC/VBIAS VSMP MCLK
CL
RS VS TIMING CONTROL
R G B 8
WM8141 OFFSET DAC + PGA
8
OFFSET MUX
RINP
RLC
INPUT MUX
CDS
R G B
+ I/P SIGNAL POLARITY ADJUST
12-BIT ADC
DATA I/O PORT
OP[11:0]
GINP
RLC
PGA MUX
BINP
RLC
RLC DAC
4
CONFIGURABLE SERIAL/ PARALLEL CONTROL INTERFACE
SEN/STB SCK/RNW SDI/DNA RLC/ACYC
Figure 17 Signal Path When in Line-by-Line Mode In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be autocycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit. The multiplexers change on the first MCLK rising edge after RLC/ACYC is taken high. Alternatively, all three multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0] to select the desired colour. It is also possible for the input multiplexer to be controlled separately from the PGA and Offset multiplexers. Table 4 describes all the multiplexer selection modes that are possible. FME 0 0 1 ACYCNRLC 0 1 0 NAME Internal, no force mux Auto-cycling, no force mux Internal, force mux Auto-cycling, force mux DESCRIPTION Input mux, offset and gain registers determined by internal register bits INTM1, INTM0. Input mux, offset and gain registers auto-cycled, RINP GINP BINP RINP... on RLC/ACYC pulse. Input mux selected from internal register bits FM1, FM0; Offset and gain registers selected from internal register bits INTM1, INTM0. Input mux selected from internal register bits FM1, FM0; Offset and gain registers auto-cycled, RINP GINP BINP RINP... on RLC/ACYC pulse.
1
1
Table 4 Colour Selection Description in Line-by-Line Mode
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OPERATING MODES
Production Data
Table 5 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE MAX SAMPLE RATE 2MSPS SENSOR INTERFACE DESCRIPTION The 3 input channels are sampled in parallel. The signal is then gain and offset adjusted before being multiplexed into a single data stream and converted by the ADC, giving an output data rate of 6MSPS max. As mode 1 except: Only one input channel at a time is continuously sampled. Identical to mode 2 TIMING REQUIREMENTS MCLK max MCLK: VSMP ratio is 6:1 REGISTER CONTENTS WITH CDS SetReg1: 03(hex) REGISTER CONTENTS WITHOUT CDS SetReg1: 01(hex)
1
Colour Pixel-by-Pixel
Yes
2
Monochrome/ Colour Line-by-Line
Yes
2MSPS
MCLK max MCLK: VSMP ratio is 6:1 MCLK max MCLK: VSMP ratio is 3:1
SetReg1: 07(hex)
SetReg1: 05(hex)
3
Fast Monochrome/ Colour Line-by-Line
Yes
4MSPS
Identical to mode 2 plus SetReg3: bits 5:4 must be set to 0(hex) CDS not possible
Identical to mode 2
4
Maximum speed Monochrome/ Colour Line-by-Line Slow Colour
No
6MSPS
Identical to mode 2
MCLK max MCLK: VSMP ratio is 2:1 MCLK max MCLK: VSMP ratio is 2n:1, n 4 MCLK max MCLK: VSMP ratio is 2n:1, n 4
SetReg1: 45(hex)
5
Yes
1.5MSPS
Identical to mode 1
Identical to mode 1
Identical to mode 1
6
Slow Monochrome/ Colour Line-by-Line
Yes
1.5MSPS
Identical to mode 2
Identical to mode 2
Identical to mode 2
Table 5 WM8141 Operating Modes Notes: 1. 2. 3. In Monochrome mode, SetReg3 bits 7:6 determine which input is to be sampled. For Colour Line-by-Line, set control bit LINEBYLINE. For input selection, refer to Table 4, Colour Selection Description in Line-by-Line Mode. MCLK max = 12MHz at AVDD = 5V, MCLK max = 8MHz at AVDD = 3.3V.
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WM8141
OPERATING MODE TIMING DIAGRAMS
The following diagrams show 12-bit parallel format output and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 5. The diagrams are identical for both CDS and non-CDS operation. Outputs from RINP, GINP and BINP are shown as R, G and B respectively. X denotes invalid data.
16.5 MCLK PERIODS
MCLK VSMP
INPUT VIDEO OP[11:0] (DEL = 00) OP[11:0] (DEL = 01)
R G B R G B R G B R G B R G B
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
OP[11:0] (DEL = 10)
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
OP[11:0] (DEL = 11)
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
Figure 18 Mode 1 Operation
16.5 MCLK PERIODS
MCLK VSMP
INPUT VIDEO OP[11:0] (DEL = 00) OP[11:0] (DEL = 01)
R X X R X X R X X R X X R
X
R
X
X
R
X
X
R
X
X
R
X
X
OP[11:0] (DEL = 10)
X
X
R
X
X
R
X
X
R
X
X
R
X
OP[11:0] (DEL = 11)
R
X
X
R
X
X
R
X
X
R
X
X
R
Figure 19 Mode 2 Operation
23.5 MCLK PERIODS
MCLK VSMP INPUT VIDEO OP[11:0] (DEL = 00) OP[11:0] (DEL = 01) OP[11:0] (DEL = 10) OP[11:0] (DEL = 11)
R R R R R R R R R R R R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Figure 20 Mode 3 Operation
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16.5 MCLK PERIODS
Production Data
MCLK VSMP INPUT VIDEO OP[11:0] (DEL = 00) OP[11:0] (DEL = 01) OP[11:0] (DEL = 10) OP[11:0] (DEL = 11)
R R R R R R R R R R R R R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Figure 21 Mode 4 Operation
16.5 MCLK PERIODS
MCLK VSMP
INPUT VIDEO OP[11:0] (DEL = 00) OP[11:0] (DEL = 01) OP[11:0] (DEL = 10) OP[11:0] (DEL = 11)
X R G B X R G B X R G B X R G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
X
R
G
B
Figure 22 Mode 5 Operation (MCLK:VSMP Ratio = 8:1)
16.5 MCLK PERIODS
MCLK VSMP
INPUT VIDEO OP[11:0] (DEL = 00) OP[11:0] (DEL = 01) OP[11:0] (DEL = 10) OP[11:0] (DEL = 11)
X R X X X R X X X R X X X
X
X
R
X
X
X
R
X
X
X
R
X
X
X
X
X
R
X
X
X
R
X
X
X
R
X
R
X
X
X
R
X
X
X
R
X
X
X
R
Figure 23 Mode 6 Operation (MCLK:VSMP Ratio = 8:1)
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DEVICE CONFIGURATION
REGISTER MAP
The following table describes the location of each control bit used to determine the operation of the WM8141. The register map is programmed by writing (in serial or parallel) the required codes to the appropriate addresses.
ADDRESS 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 100000 100001 100010 100011 101000 101001 101010 101011 Setup Reg 1 Setup Reg 2 Setup Reg 3 Software Reset Auto-cycle Reset Setup Reg 4 Revision Number Setup Reg 5 Setup Reg 6 Reserved Reserved Reserved DAC Value (Red) DAC Value (Green) DAC Value (Blue) DAC Value (RGB) PGA Gain (Red) PGA Gain (Green) PGA Gain (Blue) PGA Gain (RGB) DESCRIPTION DEF (hex) 03 20 1F 00 00 00 41 00 00 00 00 00 80 80 80 80 00 00 00 00 RW RW RW W W RW R RW RW RW RW RW RW RW RW W RW RW RW W 0 0 0 0 0 DAC[7] DAC[7] DAC[7] DAC[7] PGA[7] PGA[7] PGA[7] PGA[7] 0 0 0 0 0 DAC[6] DAC[6] DAC[6] DAC[6] PGA[6] PGA[6] PGA[6] PGA[6] 0 0 0 0 0 DAC[5] DAC[5] DAC[5] DAC[5] PGA[5] PGA[5] PGA[5] PGA[5] POSNNEG 0 0 0 0 DAC[4] DAC[4] DAC[4] DAC[4] PGA[4] PGA[4] PGA[4] PGA[4] VDEL[2] SELDIS[3] 0 0 0 DAC[3] DAC[3] DAC[3] DAC[3] PGA[3] PGA[3] PGA[3] PGA[3] VDEL[1] SELDIS [2] 0 0 0 DAC[2] DAC[2] DAC[2] DAC[2] PGA[2] PGA[2] PGA[2] PGA[2] VDEL[0] SELDIS[1] 0 0 0 DAC[1] DAC[1] DAC[1] DAC[1] PGA[1] PGA[1] PGA[1] PGA[1] VSMPDET SELDIS[0] 0 0 0 DAC[0] DAC[0] DAC[0] DAC[0] PGA[0] PGA[0] PGA[0] PGA[0] FM[1] FM[0] INTM[1] INTM[0] RLCINT FME ACYCNRLC LINEBYLINE DEL[1] CHAN[1] RW b7 b6 MODE4 DEL[0] CHAN[0] b5 PGAFS[1] RLCDACRNG CDSREF [1] b4 PGAFS[0] 0 CDSREF [0] BIT b3 SELPD VRLCEXT RLCV[3] b2 MONO INVOP RLCV[2] b1 CDS MUXOP[1] RLCV[1] b0 EN MUXOP[0] RLCV[0]
Table 6 Register Map
REGISTER MAP DESCRIPTION
The following table describes the function of each of the control bits shown in Table 6. REGISTER Setup Register 1 BIT NO 0 1 2 3 5:4 BIT NAME(S) EN CDS MONO SELPD PGAFS[1:0] DEFAULT 1 1 0 0 00 DESCRIPTION Global power down: 0 = complete power down, 1 = fully active. Select correlated double sampling mode: 0 = single ended mode, 1 = CDS mode. Mono/colour select: 0 = colour, 1 = monochrome operation. Selective power down: 0 = no individual control, 1 = individual blocks can be disabled (controlled by SELDIS[3:0]). Offsets PGA output to optimise the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 00 = Zero output (use for bipolar video) 01 = Zero output 6 MODE4 0 10 = Full-scale positive output (use for negative going video) 11 = Full-scale negative output (use for positive going video)
Required when operating in MODE4: 0 = other modes, 1 = MODE4.
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REGISTER Setup Register 2 BIT NO 1:0 BIT NAME(S) MUXOP[1:0] DEFAULT 0 DESCRIPTION Determines the output data format. 00 = 12-bit output 01 = 8-bit multiplexed (8+4 bits) 2 INVOP 0
Production Data
10 = 6-bit multiplexed mode (6+6 bits) 11 = 4-bit multiplexed mode (4+4+4 bits)
Digitally inverts the polarity of output data. 0 = negative going video gives negative going output. 1 = negative-going video gives positive going output data. When set powers down the RLCDAC, changing its output to Hi-Z, allowing VRLC to be externally driven. Sets the output range of the RLCDAC. 0 = RLCDAC ranges from 0 to AVDD (approximately). 1 = RLCDAC ranges from 0 to VRT (approximately). Sets the output latency in ADC clock periods. 1 ADC clock period = 2 MCLK periods except in mode 3 where 1 ADC clock period = 3 MCLK periods. 00 = Minimum latency 01 = Delay by one ADC clock period 10 = Delay by two ADC clock periods 11 = Delay by three ADC clock periods
3 5
VRLCEXT RLCDACRNG
0 1
7:6
DEL[1:0]
00
Setup Register 3
3:0
RLCV[3:0]
1111
Controls RLCDAC driving VRLC pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. CDS mode reset timing adjust. 00 = Advance 1 MCLK period 01 = Normal 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods 10 = Blue channel select 11 = Reserved
5:4
CDSREF[1:0]
01
7:6
CHAN[1:0]
00
Monochrome mode channel select. 00 = Red channel select 01 = Green channel select
Software Reset Auto-cycle Reset Setup Register 4 0 LINEBYLINE 0
Any write to Software Reset causes all cells to be reset. Any write to Auto-cycle Reset causes the auto-cycle counter to reset to RINP. Selects line by line operation 0 = normal operation, 1 = line by line operation. When line by line operation is selected MONO is forced to 1 and CHAN[1:0] to 00 internally, ensuring that the correct internal timing signals are produced. Green and Blue PGAs are also disabled to save power. When LINEBYLINE = 0 this bit has no effect. When LINEBYLINE = 1 this bit determines the function of the RLC/ACYC input pin and the input multiplexer and offset/gain register controls. 0 = RLC/ACYC pin enabled for Reset Level Clamp. Internal selection of input and gain/offset multiplexers. 1 = Auto-cycling enabled by pulsing the RLC/ACYC input pin. See Table 4, Colour Selection Description in Line-by-Line Mode for colour selection mode details. When auto-cycling is enabled, the RLC/ACYC pin cannot be used for reset level clamping. The RLCINT bit may be used instead. When LINEBYLINE = 0 this bit has no effect. When LINEBYLINE = 1 this bit controls the input force mux mode: 0 = No force mux, 1 = Force mux mode. Forces the input mux to be selected by FM[1:0] separately from gain and offset multiplexers. See Table 4 for details. When LINEBYLINE = 1 and ACYCNRLC = 1 this bit is used to determine whether Reset Level Clamping is used. 0 = RLC disabled, 1 = RLC enabled. Colour selection bits used in internal modes. See Table 4 for details. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. Colour selection bits used in input force mux modes. See Table 4 for details. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.
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ACYCNRLC
0
2
FME
0
3
RLCINT
0
5:4 7:6
INTM[1:0] FM[1:0]
00 00
WOLFSON MICROELECTRONICS LTD
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Production Data REGISTER Setup Register 5 BIT NO 0 BIT NAME(S) VSMPDET DEFAULT 0 DESCRIPTION
WM8141
0 = Normal operation, signal on VSMP input pin is applied directly to Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronisation pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block. When VSMPDET = 0 these bits have no effect. When VSMPDET = 1 these bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 16 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit, for details. When VSMPDET = 0 this bit has no effect. When VSMPDET = 1 this bit controls whether positive or negative edges are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 15 for further details. Selective power disable register - activated when SELPD = 1. Each bit disables respective function when 1, enabled when 0. SELDIS[0] = Red CDS, PGA SELDIS[1] = Green CDS, PGA SELDIS[2] = Blue CDS, PGA SELDIS[3] = ADC
3:1
VDEL[2:0]
000
4
POSNNEG
0
Setup Register 6
3:0
SELDIS[3:0]
0
Table 7 Register Control Bits
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WM8141 APPLICATIONS RECOMMENDATIONS
INTRODUCTION
Production Data
The WM8141 is a mixed signal device, therefore careful PCB layout is required. The following section contains PCB layout guidelines, which are recommended for optimal performance from the WM8141, and some typical applications circuits.
PCB LAYOUT
1) 2) 3) 4) Use separate analogue and digital power and ground planes. The analogue and digital ground planes should be connected as close as possible to, or underneath, the WM8141. Place all supply decoupling capacitors as close as possible to their respective supply pins and provide a low impedance path from the capacitors to the appropriate ground. Avoid noise on AGND, pin 13. Avoid noise on reference pins VRT, VRB and VRX. Place the decoupling capacitors as close as possible to these pins and provide a low impedance path from the capacitors to analogue ground. Input signals should be screened from each other and from other sources of noise to avoid cross- talk and interference. Minimise load capacitance on digital outputs. Capacitive loads of greater than 20pF will degrade performance. Use buffers if necessary and keep tracks short.
5) 6)
TYPICAL APPLICATIONS DIAGRAMS
The WM8141 is intended to be used in three types of architecture. * * * Monochrome Colour Pixel-By-Pixel Colour Line-By-Line
Each of these architectures is outlined in this section. The output from a CCD sensor usually has a high impedance and must therefore be buffered as close to the sensor as possible. The sensor manufacturers' datasheets specify the buffer circuit to use. Initially, the designer must decide if CDS and RLC are to be used. The WM8141 supports both of these functions and Wolfson recommend using both CDS and pixel-by-pixel RLC for optimal performance. In this case a low value a.c. coupling capacitor is required between the sensor and the WM8141. Experiments have shown that a 100pF capacitor is the optimum value to use, however this may vary for particular applications depending on speed of operation and PCB layout.
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Production Data
WM8141
MONOCHROME CCD
S E N S O R
C VOUT BUFFER See sensor datasheet for details RINP
WM8141
INCLUDING RECOMMENDED EXTERNAL COMPONENTS
CLOCKS
DATA
SYSTEM ASIC
CONTROL I/F SENSOR TIMING
Maximum pixel rate = 1.5Mpixels/second (Mode 6) Maximum pixel rate = 2Mpixels/second (Mode 2) Maximum pixel rate = 4Mpixels/second (Mode 3) Maximum pixel rate = 6Mpixels/second (Mode 4)
Figure 24 Block Diagram of Monochrome CCD Application, AC Coupled REGISTER NAME Set-up register 1 ADDRESS 000001 2F SETTING HEX BINARY 0010 1111 EN = 1: Device enabled; CDS = 1: CDS enabled; MONO = 1: Monochrome operation; SELPD = 1: Selective power down possible; PGAFS[1:0] = 10: ADC range optimised for negative going video; MODE4 = 0: Only set when 2:1 MCLK:VSMP ratio required (mode 4). MUXOP[1:0] = 00: 12-bit parallel output; INVOP = 0: Output data not inverted; VRLCEXT = 0: RLCDAC required to provide reset level clamp voltage since sensor is AC coupled; RLCDACRNG = 1: RLCDAC range is 0V to VRT; DEL[1:0] = 00: Default latency. RLCV[3:0] = 1111: RLCDAC full scale voltage; CDSREF[1:0] = 01: Default reset sample position; CHAN[1:0] = 00: Red channel selected. Line-by-line mode not used so this register is not required. Only used if programmable VSMP circuit is required. SELDIS[3:0] = 0110: Disable green and blue channels to reduce power. NOTE
Set-up register 2
000010
20
0010 0000
Set-up register 3
000011
1F
0001 1111
Set-up register 4 Set-up register 5 Set-up register 6 Table 8
000101 001000 001001
00 00 06
0000 0000 0000 0000 0000 0110
Typical Control Register Settings for Figure 24 (CDS, Negative-Going CCD Video Signal, MCLK:VSMP = 2:1/3:1/6:1/8:1)
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WM8141
COLOUR PIXEL-BY-PIXEL
Production Data
CR
S E N S O R
R
BUFFER CG
RINP
CLOCKS
WM8141
GINP INCLUDING RECOMMENDED EXTERNAL COMPONENTS DATA
G
BUFFER CB
B
BUFFER See sensor datasheet for details.
BINP
CONTROL I/F
SYSTEM ASIC
SENSOR TIMING
Maximum pixel rate = 1.5Mpixels/second (Mode 5) Maximum pixel rate = 2Mpixels/second (Mode 1)
Figure 25 Block Diagram of Colour Pixel-By-Pixel Application, AC Coupled REGISTER NAME Set-up register 1 ADDRESS 000001 13 SETTING HEX BINARY 0010 0011 EN = 1: Device enabled; CDS = 1: CDS enabled; MONO = 0: Colour operation; SELPD = 0: No selective power down; PGAFS[1:0] = 10: ADC range optimised for negative going video; MODE4 = 0: Not required for colour. MUXOP[1:0] = 00: 12-bit parallel output; INVOP = 0: Output data not inverted; VRLCEXT = 0: RLCDAC required to provide reset level clamp voltage since sensor is AC coupled; RLCDACRNG = 1: RLCDAC range is 0V to VRT; DEL[1:0] = 00: Default latency RLCV[3:0] = 1111: RLCDAC full scale voltage; CDSREF[1:0] = 01: Default reset sample position; CHAN[1:0] = XX: Colour mode so not required. Line-by-Line mode not used so this register is not required. Only used if programmable VSMP circuit is required. All channels enabled. NOTE
Set-up register 2
000010
20
0010 0000
Set-up register 3
000011
1F
XX01 1111
Set-up register 4 Set-up register 5 Set-up register 6 Table 9
000101 001000 001001
00 00 00
0000 0000 0000 0000 0000 0000
Typical Control Register Settings for Figure 25 (CDS, Negative-Going CCD Video Signal, MCLK:VSMP = 6:1/8:1)
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Production Data
WM8141
COLOUR LINE-BY-LINE
S E N S O R
C VOUT BUFFER See sensor datasheet for details RINP
WM8141
INCLUDING RECOMMENDED EXTERNAL COMPONENTS
CLOCKS
DATA
SYSTEM ASIC
CONTROL I/F SENSOR TIMING
Maximum pixel rate = 1.5Mpixels/second (Mode 6) Maximum pixel rate = 2Mpixels/second (Mode 2) Maximum pixel rate = 4Mpixels/second (Mode 3) Maximum pixel rate = 6Mpixels/second (Mode 4)
Figure 26 Block Diagram Of Colour Line-By-Line Application, AC Coupled REGISTER NAME Set-up register 1 ADDRESS 000001 23 SETTING HEX BINARY 0010 0X11 EN = 1: Device enabled; CDS = 1: CDS enabled; MONO = X: Forced internally when LINEBYLINE is set; SELPD = 0: No selective power down; PGAFS[1:0] = 10: ADC range optimised for negative going video; MODE4 = 0: set high if MCLK:VSMP ratio of 2:1 is required. MUXOP[1:0] = 00: 12-bit parallel output; INVOP = 0: Output data not inverted; VRLCEXT = 0: RLCDAC required to provide reset level clamp voltage since sensor is AC coupled; RLCDACRNG = 1: RLCDAC range is 0V to VRT; DEL[1:0] = 00: Default latency. RLCV[3:0] = 1111: RLCDAC full scale voltage; CDSREF[1:0] = 01: Default reset sample position; CHAN[1:0] = XX: Colour mode so not required. LINEBYLINE = 1: Line by line mode selected; ACYCNRLC = 1: Auto-cycling required; FME = 1: Input mux controlled by FME bits; RLCINT = 1: RLC performed on every pixel; INTM[1:0] = XX: PGA/Offset multiplexers controlled by auto-cycling so these bits have no effect; FME[1:0] = 00: Controls input multiplexer to select red channel. Only used if programmable VSMP circuit is required. Green and blue channels are automatically powered down when LINEBYLINE = 1. NOTE
Set-up register 2
000010
20
0010 0000
Set-up register 3
000011
1F
01 1111
Set-up register 4
000101
0B
00XX 1111
Set-up register 5 Set-up register 6
001000 001001
00 00
0000 0000 0000 0000
Table 10 Typical Control Register Settings for Figure 26 (CDS, Negative-Going CCD Video Signal, MCLK/VSMP = 2:1/3:1/6:1/8:1)
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PD Rev 3.0 October 2000
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WM8141 RECOMMENDED EXTERNAL COMPONENTS
DVDD 14 32 C1 C2 AVDD 12 C3 DGND AGND 21 RINP GINP BINP VRT VRX VRB 16 17 15 C6 18 C9 VRLC/VBIAS C7 C8 C4 C5 AGND AVDD AGND 13 DVDD1 DVDD2 DGND 29
Production Data
Video Inputs
20 19
WM8141
AGND 28 MCLK VSMP RLC/ACYC OP[11]/SDO OP[10] OP[9] OP[8] 25 24 SCK/RNW SDI/DNA SEN/STB OP[7] OP[6] OP[5] OP[4] 22 11 NOTES: 1. C1-9 should be fitted as close to WM8141 as possible. 2. AGND and DGND should be connected as close to WM8141 as possible. OEB NRESET OP[3] OP[2] OP[1] OP[0] 10 9 8 7 6 5 4 3 2 1 31 30
AGND
Timing Signals
27 26
DVDD + C10 + C11
AVDD + C12
Interface Controls
23
Output Data Bus
DGND
AGND
Figure 27 External Components Diagram COMPONENT REFERENCE C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 SUGGESTED VALUE 100nF 100nF 100nF 10nF 1F 100nF 100nF 100nF 100nF 10F 10F 10F De-coupling for DVDD1. De-coupling for DVDD2. De-coupling for AVDD. High frequency de-coupling between VRT and VRB. Low frequency de-coupling between VRT and VRB (non-polarised). De-coupling for VRB. De-coupling for VRX. De-coupling for VRT. De-coupling for VRLC. Reservoir capacitor for DVDD. Reservoir capacitor for DVDD. Reservoir capacitor for AVDD. DESCRIPTION
Table 11 External Components Descriptions
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Production Data
WM8141
PACKAGE DIMENSIONS
FT: 32 PIN TQFP (7 x 7 x 1.4 mm) DM002.B
b
e
17
24
25
16
E1
E
32
9
1
8
D1 D c
L A A2 A1
-Cccc C
SEATING PLANE
Symbols A A1 A2 b c D D1 E E1 e L ccc REF:
Dimensions (mm) MIN NOM MAX --------1.60 0.05 ----0.15 1.35 1.40 1.45 0.30 0.37 0.45 0.09 ----0.20 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.80 BSC 0.45 0.60 0.75 o o o 0 3.5 7 Tolerances of Form and Position 0.10 JEDEC.95, MS-026
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = BBA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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31

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